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<div class="header">
  <div class="headertitle"><div class="title">OCTOSPI_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a></div></div></div>
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<div class="contents">

<p>OCTO Serial Peripheral Interface.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>OCTO Serial Peripheral Interface. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="acbda2c2cf5374ccfd85f0c59490fe14a" name="acbda2c2cf5374ccfd85f0c59490fe14a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acbda2c2cf5374ccfd85f0c59490fe14a">&#9670;&#160;</a></span>ABR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::ABR</td>
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<p>OCTOSPI Alternate Bytes register, Address offset: 0x120 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2afc2358d015b00bdc9ae1d19775fc39">&#9670;&#160;</a></span>AR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::AR</td>
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<p>OCTOSPI Address register, Address offset: 0x048 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3fa9d712bb263f5e5138df69b2e3bd00">&#9670;&#160;</a></span>CCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::CCR</td>
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<p>OCTOSPI Communication Configuration register, Address offset: 0x100 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac71d27abd195793719c5a5991191e8a4">&#9670;&#160;</a></span>CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::CR</td>
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<p>OCTOSPI Control register, Address offset: 0x000 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad55538f7543126fa1fdb2d0ad9d75849">&#9670;&#160;</a></span>DCR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::DCR1</td>
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<p>OCTOSPI Device Configuration register 1, Address offset: 0x008 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a961f31cc49d83c8e42550eb21d9c8a61">&#9670;&#160;</a></span>DCR2</h2>

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<p>OCTOSPI Device Configuration register 2, Address offset: 0x00C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae7e093d03f39bff4c59db5ea5132dabb">&#9670;&#160;</a></span>DCR3</h2>

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<p>OCTOSPI Device Configuration register 3, Address offset: 0x010 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a236b297d03ff9b84c6ac71e18b09e4f1">&#9670;&#160;</a></span>DCR4</h2>

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<p>OCTOSPI Device Configuration register 4, Address offset: 0x014 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a18bbd693bea6be022533707df2438fdc">&#9670;&#160;</a></span>DLR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::DLR</td>
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<p>OCTOSPI Data Length register, Address offset: 0x040 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af349e5d2d8db8719023ed2109676f720">&#9670;&#160;</a></span>DR</h2>

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<p>OCTOSPI Data register, Address offset: 0x050 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa542fba306d6f4fca93c83155901e5f9">&#9670;&#160;</a></span>FCR</h2>

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<p>OCTOSPI Flag Clear register, Address offset: 0x024 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6ad289f43ae45a78a69c5eabce275287">&#9670;&#160;</a></span>HLCR</h2>

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<p>OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aef9bc968c5d50c955027702a8a687de7">&#9670;&#160;</a></span>HWCFGR</h2>

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<p>OCTOSPI HW Configuration register, Address offset: 0x3F0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4cde4c505402e2ebb6775f602d859116">&#9670;&#160;</a></span>ID</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::ID</td>
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<p>OCTOSPI Identification register, Address offset: 0x3F8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a05ea31567da177f80d31e822bd555e8b">&#9670;&#160;</a></span>IR</h2>

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<p>OCTOSPI Instruction register, Address offset: 0x110 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6b37c4aeb2d2b387fb79a6af2454d8d3">&#9670;&#160;</a></span>LPTR</h2>

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<p>OCTOSPI Low Power Timeout register, Address offset: 0x130 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae83a4795255896d4a015d3526b7df762">&#9670;&#160;</a></span>MID</h2>

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<p>OCTOPSI HW Magic ID register, Address offset: 0x3FC </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac4d100c3a19d687362814b9975f61db5">&#9670;&#160;</a></span>PIR</h2>

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<p>OCTOSPI Polling Interval register, Address offset: 0x090 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1bb4b32c85c7d4a2c52dd12fb9fbc8e3">&#9670;&#160;</a></span>PSMAR</h2>

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<p>OCTOSPI Polling Status Match register, Address offset: 0x088 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aceec86c14c2af88f8c441a23d27c0c22">&#9670;&#160;</a></span>PSMKR</h2>

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<p>OCTOSPI Polling Status Mask register, Address offset: 0x080 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab4a777b2a2635f47a26ab4328e8d4a85">&#9670;&#160;</a></span>RESERVED</h2>

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<p>Reserved, Address offset: 0x004 </p>

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<p>Reserved, Address offset: 0x018-0x01C </p>

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<p>Reserved, Address offset: 0x10C </p>

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<a id="a6027570a8b87a6843d69209f5e08c759" name="a6027570a8b87a6843d69209f5e08c759"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6027570a8b87a6843d69209f5e08c759">&#9670;&#160;</a></span>RESERVED11</h2>

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<p>Reserved, Address offset: 0x114-0x11C </p>

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<a id="a8a7c7b5da8ab25a785528330a2930d3f" name="a8a7c7b5da8ab25a785528330a2930d3f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8a7c7b5da8ab25a785528330a2930d3f">&#9670;&#160;</a></span>RESERVED12</h2>

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<p>Reserved, Address offset: 0x124-0x12C </p>

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<a id="a41c9fec3b5915ebb84e0c65bd0f6112c" name="a41c9fec3b5915ebb84e0c65bd0f6112c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a41c9fec3b5915ebb84e0c65bd0f6112c">&#9670;&#160;</a></span>RESERVED13</h2>

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<p>Reserved, Address offset: 0x134-0x13C </p>

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<a id="a4297eefcc58cebb4137aa7aa8b3273e8" name="a4297eefcc58cebb4137aa7aa8b3273e8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4297eefcc58cebb4137aa7aa8b3273e8">&#9670;&#160;</a></span>RESERVED14</h2>

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<p>Reserved, Address offset: 0x144 </p>

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<a id="a684105027411e5937275840c83618729" name="a684105027411e5937275840c83618729"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a684105027411e5937275840c83618729">&#9670;&#160;</a></span>RESERVED15</h2>

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<p>Reserved, Address offset: 0x14C </p>

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<a id="aa4f4afe2981ea4f9516428393ffc3b0e" name="aa4f4afe2981ea4f9516428393ffc3b0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa4f4afe2981ea4f9516428393ffc3b0e">&#9670;&#160;</a></span>RESERVED16</h2>

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<p>Reserved, Address offset: 0x154-0x15C </p>

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<a id="a9af5040cff1d5d7cc881da5cf9da79bc" name="a9af5040cff1d5d7cc881da5cf9da79bc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9af5040cff1d5d7cc881da5cf9da79bc">&#9670;&#160;</a></span>RESERVED17</h2>

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<p>Reserved, Address offset: 0x164-0x17C </p>

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<a id="a50e4dd6d85fc5aa3d157c6d101da2ae8" name="a50e4dd6d85fc5aa3d157c6d101da2ae8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a50e4dd6d85fc5aa3d157c6d101da2ae8">&#9670;&#160;</a></span>RESERVED18</h2>

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<p>Reserved, Address offset: 0x184 </p>

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<a id="a5f9bb07a7f90f6c9629f2c8a0cbcd2ad" name="a5f9bb07a7f90f6c9629f2c8a0cbcd2ad"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5f9bb07a7f90f6c9629f2c8a0cbcd2ad">&#9670;&#160;</a></span>RESERVED19</h2>

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<p>Reserved, Address offset: 0x18C </p>

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<a id="af8fcdc41ec1e2b222e804dab9970cd10" name="af8fcdc41ec1e2b222e804dab9970cd10"></a>
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<p>Reserved, Address offset: 0x028-0x03C </p>

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<p>Reserved, Address offset: 0x194-0x19C </p>

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<a id="afb0d39d49dab12fb3db244623f8ac0c9" name="afb0d39d49dab12fb3db244623f8ac0c9"></a>
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<p>Reserved, Address offset: 0x1A4-0x1FC </p>

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<a id="a17106bf864619eeb7a9f670e1882681a" name="a17106bf864619eeb7a9f670e1882681a"></a>
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<p>Reserved, Address offset: 0x204-0x3EC </p>

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<p>Reserved, Address offset: 0x044 </p>

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<a id="a03509b1d3c60ccbb7d1cde25b08fcce8" name="a03509b1d3c60ccbb7d1cde25b08fcce8"></a>
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<p>Reserved, Address offset: 0x04C </p>

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<a id="af6839968188cfe826d6672fad77e7be4" name="af6839968188cfe826d6672fad77e7be4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af6839968188cfe826d6672fad77e7be4">&#9670;&#160;</a></span>RESERVED5</h2>

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<p>Reserved, Address offset: 0x054-0x07C </p>

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<a id="a1c1eea519097a483369b16d579213b21" name="a1c1eea519097a483369b16d579213b21"></a>
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<p>Reserved, Address offset: 0x084 </p>

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<a id="a63540ebe30220332fd765f775ffd0aa0" name="a63540ebe30220332fd765f775ffd0aa0"></a>
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<p>Reserved, Address offset: 0x08C </p>

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<a id="a534fdd219a20c191e0a451b1b164ee1c" name="a534fdd219a20c191e0a451b1b164ee1c"></a>
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<p>Reserved, Address offset: 0x094-0x0FC </p>

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<a id="aff35db3f551e942d4701624c14554afb" name="aff35db3f551e942d4701624c14554afb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aff35db3f551e942d4701624c14554afb">&#9670;&#160;</a></span>RESERVED9</h2>

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<p>Reserved, Address offset: 0x104 </p>

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<a id="af2d07941b01f96222d175a411a99cbc5" name="af2d07941b01f96222d175a411a99cbc5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af2d07941b01f96222d175a411a99cbc5">&#9670;&#160;</a></span>SR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::SR</td>
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<p>OCTOSPI Status register, Address offset: 0x020 </p>

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<a id="abd076236680eeed099c89f7443e23880" name="abd076236680eeed099c89f7443e23880"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abd076236680eeed099c89f7443e23880">&#9670;&#160;</a></span>TCR</h2>

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<p>OCTOSPI Timing Configuration register, Address offset: 0x108 </p>

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<a id="adad6a0a30021b2b7277d2ab520767e25" name="adad6a0a30021b2b7277d2ab520767e25"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adad6a0a30021b2b7277d2ab520767e25">&#9670;&#160;</a></span>VER</h2>

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<p>OCTOSPI Version register, Address offset: 0x3F4 </p>

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<a id="a5f2343ad009c5df8a20651333a26da6d" name="a5f2343ad009c5df8a20651333a26da6d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5f2343ad009c5df8a20651333a26da6d">&#9670;&#160;</a></span>WABR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WABR</td>
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<p>OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 </p>

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<a id="a72e85208b55696102636bdf50e58dc98" name="a72e85208b55696102636bdf50e58dc98"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a72e85208b55696102636bdf50e58dc98">&#9670;&#160;</a></span>WCCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WCCR</td>
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<p>OCTOSPI Write Communication Configuration register, Address offset: 0x180 </p>

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<a id="afd4ca0392882475e1d8ff0461d97362e" name="afd4ca0392882475e1d8ff0461d97362e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afd4ca0392882475e1d8ff0461d97362e">&#9670;&#160;</a></span>WIR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WIR</td>
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<p>OCTOSPI Write Instruction register, Address offset: 0x190 </p>

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<a id="ac5f058bd9896d8bfc4fa3206d1e1f755" name="ac5f058bd9896d8bfc4fa3206d1e1f755"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac5f058bd9896d8bfc4fa3206d1e1f755">&#9670;&#160;</a></span>WPABR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WPABR</td>
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<p>OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 </p>

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<a id="a49e9d597b1d04c06107e6f458a893494" name="a49e9d597b1d04c06107e6f458a893494"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a49e9d597b1d04c06107e6f458a893494">&#9670;&#160;</a></span>WPCCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WPCCR</td>
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<p>OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 </p>

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<a id="ac83773556b0dc04b2a3bda3820e1a258" name="ac83773556b0dc04b2a3bda3820e1a258"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac83773556b0dc04b2a3bda3820e1a258">&#9670;&#160;</a></span>WPIR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WPIR</td>
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<p>OCTOSPI Wrap Instruction register, Address offset: 0x150 </p>

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<a id="acc4f24b481b265e2b9e1de1cdbcc7010" name="acc4f24b481b265e2b9e1de1cdbcc7010"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acc4f24b481b265e2b9e1de1cdbcc7010">&#9670;&#160;</a></span>WPTCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WPTCR</td>
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<p>OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 </p>

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<a id="a8386b6515a1abf5b6c01506469779695" name="a8386b6515a1abf5b6c01506469779695"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8386b6515a1abf5b6c01506469779695">&#9670;&#160;</a></span>WTCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCTOSPI_TypeDef::WTCR</td>
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<p>OCTOSPI Write Timing Configuration register, Address offset: 0x188 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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